TILE Gx™ Processor Block Diagram Photo: Tilera Corporation

SAN JOSE, Calif., Oct. 26, 2009 - Tilera® Corporation today announced its new TILE-Gx™ family - four new processors from Tilera including the world's first 100-core processor: the TILE-Gx100™.

The TILE-Gx100 offers the highest performance of any microprocessor yet announced by a factor of four. Moreover, the entire TILE-Gx family raises the bar for performance-per-watt to new levels with ten times better compute efficiency compared to Intel's next generation Westmere processor. And Tilera has simplified many-core programming with its breakthrough Multicore Development Environment™ (MDE) together with a growing ecosystem of operating system and software partners to enable rapid product deployment.

TILE64™ Processor Block Diagram. Photo: Tilera Corporation

The TILE-Gx family - available with 16, 36, 64 and 100 cores - employs Tilera's unique architecture that scales well beyond the core count of traditional microprocessors.
Tilera's two-dimensional iMesh™ interconnect eliminates the need for an on-chip bus and its Dynamic Distributed Cache (DDC™) system allows each cores' local cache to be shared coherently across the entire chip.
These two key technologies enable the TILE Architecture™ performance to scale linearly with the number of cores on the chip - a feat that is currently unmatched.

TILE64™ Tile Block Diagram. Photo: Tilera Corporation

"The launch of the TILE-Gx family, including the world's first 100-core microprocessor, ushers in a new era of many-core processing. We believe this next generation of high-core count, ultra high-performance chips will open completely new computing possibilities,” said Omid Tahernia, Tilera's CEO.
“Customers will be able to replace an entire board presently using a dozen or more chips with just one of our TILE-Gx processors, greatly simplifying the system architecture and resulting in reduced cost, power consumption, and PC board area. This is truly a remarkable technology achievement.”


Leading the Evolution to Many-Core


Tilera's breakthroughs in scalable multicore computing are changing the model of computing.

Wafer picture - a sea of compute. Photo: Tilera Corporation

Many-core processors enable a wide range of new opportunities including

Consolidation of functions: A single many-core processor can absorb functions that previously required multiple processors, thus lowering system cost and providing a single software tool chain and programming model for developers.

Granularity of compute: Processing resources can be allocated to functions in precise increments, optimizing performance and saving power.

Deterministic compute: Enables processor cores to be dedicated to specific tasks, including cache-coherent islands of compute, for highly predictable performance.

TILExpress™ Card. Photo: Tilera Corporation

“At various points in microprocessor history there have been breakthroughs that have enabled significant advances in computing, such as when the barrier of single-core clock speed was overcome by the introduction of multicore,” said Sergis Mushell, principal research analyst, Gartner.
“Cloud computing and virtualization have ushered in a new era of processing power optimization and utilization, which has accelerated the roadmaps for multicore architectures and changed the paradigm from a clock frequency discussion of the past to a new discussion about number of cores and core optimization.”


About the TILE-Gx Processor Family


The TILE-Gx family, fabricated in TSMC's 40 nanometer process, operates at up to 1.5 GHz with power consumption ranging from 10 to 55 watts.
Like the TILE and TILEPro™ processors, the TILE-Gx family incorporates many cores on a single chip together with integrated memory controllers and a rich set of I/O.

TILEncore™ Card. Photo: Tilera Corporation

However the TILE-Gx device also brings together a number of new features to maximize application performance while offering the best performance-per-watt in the industry. Some of the technology highlights include:

Next-generation 64-bit core: New three-issue 64-bit core with full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.

Enhanced SIMD instruction extensions: Improved signal processing performance with a 4 MAC/cycle multiplier unit delivering up to 600 billion MACs per second, more than 12x the fastest commercial DSP.

Integrated high-performance DDR3 memory controllers: Two or four 72-bit controllers running up to 2133 MHz speeds with ECC support. Up to 1TB total capacity and powerful memory striping modes for maximum utilization.

Hardware acceleration engines: On-chip MiCA™ (Multistream iMesh Crypto Accelerator) system delivers up to 40Gbps encryption and 20Gbps full duplex compression processing, tightly coupled to the iMesh for extremely low latency and wire-speed small packet throughput. In addition, a high-performance true random number generator (RNG) and public key accelerator enable up to 50,000 RSA handshakes per second.

Packet processing accelerator: mPIPE™ (multicore Programmable Intelligent Packet Engine) system provides wire-speed packet classification, load balancing and buffer management. This flexible, C-programmable engine delivers 80 Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.


Target Markets and Availability


The TILE-Gx processor family is ideal for a wide range of markets including enterprise networking, cloud computing, multimedia and wireless infrastructure, with the TILE-Gx16™ targeting more cost-sensitive applications and the TILE-Gx100 targeting performance applications.

The TILE-Gx36 processor will be sampling in Q4 of 2010 with the other processors rolling out in the following two quarters.


Tilera Sponsors EE Times Many-Core Virtual Conference


Join Tilera for the EE Times Many-Core virtual conference on Oct. 28, 2009 from 11 a.m. to 5 p.m. Eastern to hear panelists from Tilera and other companies speak about the impending shift to many-core.

Tilera will be hosting a premier booth where it will provide further details on the TILE-Gx family and answer any questions you may have.

Register at:

www.eetimes.com/manycore/  



About Tilera


Tilera® Corporation is the industry leader in highly scalable general purpose multicore processors for networking, wireless, and multimedia infrastructure applications.

Tilera Corporation, Westborough Office, Massachusetts.  Photo: Tilera Corporation

Tilera's processors are based on its breakthrough iMesh™ architecture that scales to hundreds of RISC-based cores on a single chip.

The distributed nature, of Tilera's revolutionary architecture, and the standards-based tools, including ANSI C/C++ compiler, GNU tools and Eclipse IDE, deliver an unprecedented combination of performance, power efficiency and programming flexibility.

Tilera Corporation, San Jose Office, California. Photo: Tilera Corporation

Tilera was founded in October 2004, and now provides two product families: TILE64™ processors and TILEPro™ processors.

The company is headquartered in San Jose, Calif., with locations in Westborough, Mass., Shanghai, and Beijing.

Tilera Contact:
Tara Sims
SiliconPR for Tilera
415.310.5779
Email: tara.sims@siliconpr.com

http://tilera.com/index.php  

http://tilera.com/news_&_events/press_release_091026.php  



TILE-Gx Processors Family


The TILE-Gx™ processor family processor brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market.
This latest generation processor family features devices with 16 to 100 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network.

Each tile consists of a complete, full featured processor as well as L1 & L2 cache and a non-blocking switch that connect the tiles into the mesh. As with all Tilera processors, each tile can independently run a full operating system, or, multiple tiles taken together can run a multiprocessing OS like SMP Linux.

The TILE-Gx family processor slashes board real estate requirements and system costs by integrating a complete set of memory and I/O controllers, therefore eliminating the need for an external north bridge or south bridge.

TileDirect™ technology provides coherent I/O directly into the tile caches to deliver ultimate low-latency packet processing performance.
Tilera's DDC™ (Dynamic Distributed Cache) system for fully coherent cache across the tile array enables scalable performance for threaded and shared memory applications.

The TILE-Gx processors are programmed in ANSI standard C and C++, enabling developers to leverage their existing software investment.
Tiles can be grouped in clusters to apply the appropriate amount of horsepower to each application.
Since multiple virtualized operating system instances can be run on the TILE-Gx simultaneously, it can replace multiple CPU and DSP subsystems for both the data plane and control plane.

http://tilera.com/products/TILE-Gx.php  



Tilera Partners with JETRO to Introduce Tile Multicore Processors to Japan


SAN JOSE, Calif., Jun. 10, 2009 - Tilera® Corporation today announced its participation in the Japanese External Trade Organization's (JETRO) program for bringing businesses to Japan. Building upon its multicore processors' success in North America, Europe, China and the Middle East, Tilera has been selected to use JETRO's services and will be able to access potential business partners, recruitment companies, legal advisors, and temporary office spaces.

“We are honored to be selected by JETRO to participate in this prestigious program. We see the Japanese market as being vital to our continued growth and we see JETRO as being key to our success in Japan,” said Omid Tahernia, CEO, Tilera Corporation.
“JETRO's program simplifies many of the steps necessary to launch a business in Japan.”

Tilera offers a range of multicore processors with significant performance and power efficiency advantages for networking, multimedia, and wireless infrastructure equipment.

Tilera processors are used across multiple applications including network security, intrusion prevention, network monitoring, data compliance, DPI, L4-L7 services, video conferencing, IPTV distribution, VoD delivery, video transcoding, and wireless media gateways.

The TILEPro™ processor mitigates the challenges of high power, cooling cost, and compute density by providing equipment manufacturers with 3-4x the performance and up to 5x the performance per watt of the nearest competitor.


About Tilera


Tilera® Corporation is the industry leader in highly scalable general purpose multicore processors for networking, wireless, and multimedia infrastructure applications.

Tilera's processors are based on its breakthrough iMesh™ architecture that scales to hundreds of RISC-based cores on a single chip.
The distributed nature, of Tilera's revolutionary architecture, and the standards-based tools, including ANSI C/C++ compiler, GNU tools and Eclipse IDE, deliver an unprecedented combination of performance, power efficiency and programming flexibility.

Tilera was founded in October 2004, and now provides two product families: TILE64™ processors and TILEPro™ processors.

The company is headquartered in San Jose, Calif., with locations in Westborough, Mass., and Beijing.


About JETRO


JETRO, or Japan External Trade Organization, is a government-related organization that works to promote mutual trade and investment between Japan and the rest of the world.

Originally established in 1958 to promote Japanese exports abroad, JETRO's core focus in the 21st century has shifted toward promoting foreign direct investment into Japan and helping small to medium size Japanese firms maximize their global export potential.


Tilera Contact:

Ihab Bishara
Marketing Director
Tilera Corporation
Email: ibishara@tilera.com



Omid Tahernia

President and Chief Executive Officer

Omid Tahernia, President & CEO, Tilera Corporation. Photo: Tilera Corp.

Mr. Tahernia has twenty four years of experience in leading organizations providing systems and semiconductor solutions.
Prior to Tilera, he spent three years at Xilinx, where he started as Vice President and General Manager of a newly created DSP Division in 2004 and later served as Vice President and General Manager of the Processing Solutions Group consisting of DSP, Embedded and IP Divisions.
His responsibilities included the business and product strategy for configurable DSP and Embedded processing.
Mr. Tahernia served as a member of the Xilinx Executive team during his tenure there.

Prior to Xilinx, Mr. Tahernia spent 21 years at Motorola where he began his career in 1984 and worked in both the equipment and semiconductor segments. In his final role at Motorola Semiconductors, from May 2003 to June 2004, he served as Vice President and Director of Worldwide Strategy and Business Development for the Wireless Group.
Prior to that, from 1999 to 2003, he served as Vice President and General Manager of the Wireless and Mobile Systems Division driving a $1B wireless chipset business including baseband and application processors.
Mr. Tahernia also held various management positions in the Motorola Paging Group including technology, product development, and licensing.
His product management responsibilities included serving international markets of Japan, Asia Pacific and China.
Mr. Tahernia was recognized for his engineering excellence and received the Motorola Distinguished Innovator and Patent of the Year awards in 1993 and 1994 respectively.

Mr. Tahernia holds 13 U.S. patents, a B.S. degree in Electrical Engineering from Virginia Polytechnic Institute & State University, and an M.S.EE degree from Georgia Institute of Technology.


http://tilera.com/company/management.php